1. Automatic Integration of HDL IPs in Simulinkusing FMI and S-Function Interfaces.- 2. Towards Early Validation of Firmware-Based Power Management using Virtual Prototypes: A Constrained Random Approach.- 3. Symbolic Simulation of Dataflow Synchronous Programs with Timers.- 4. Language and Hardware Acceleration Backend for Graph Processing.- 5. Fault Analysis in Analog Circuits through Language Manipulation and Abstraction.- 6. A Methodology for Automated Consistency Checking Between Different Power-Aware Descriptions. ukryj opis